This invention relates to switched capacitor circuits or networks and more particularly to switched capacitor circuit replacements of resistors.
Switched capacitor circuits for simulating resistors are described in the references "Sampled Analog Filtering Using Switched Capacitors as Resistor Equivalents" by J. T. Caves, et. al., IEEE Journal of Solid State Circuits, Vol. 12, No. 6, pages 592-599, December, 1977; "MOS Sampled Data Recursive Filters Using Switched Capacitor Integrators" by B. J. Hosticka, et. al., IEEE Journal of Solid State Circuits, Vol. 12, No. 6, pages 600-608, December, 1977; "Switched Capacitor Filter Design Using the Bilinear z-Transform" by G. C. Temes, et. al., IEEE Transactions on Circuits and Systems, Vol. 25, No. 12, pages 1039-1044, December, 1978; "Derivation of Switched Capacitor Filters From Active-RC Prototypes" by G. C. Temes, Electronics Letters, Vol. 14, No. 12, pages 361-362, June, 1978.
Techniques for reducing the effects of parasitic capacitances in switched capacitor circuits are also described in the article "Compensation for Parasitic Capacitances in Switched-Capacitor Filters" by G. C. Temes, et. al., Electronics Letters, Vol. 15, No. 13, pages 377-379, June, 1979. A number of the switched capacitor resistors disclosed in these references are susceptible to top and/or bottom plate parasitic capacitance effects. Also, a network using at least one of the simulated resistors disclosed in these references and LDI (lossless discrete integrator) inductors of the type disclosed in the article "Switched Capacitor Filters Using Floating-Inductance Simulation Circuit" by Man Shek Lee, Electronics Letters, Vol. 15, No. 20, pages 644-645, September, 1979, requires 4-phase, rather than 2-phase, timing control signals.
An object of this invention is the provision of novel switched capacitor structures for simulating resistors.